Methods of forming wells in semiconductor devices

ABSTRACT

Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed method includes forming a trench in a surface of a substrate to define a field area, forming a first conductive type well in a first active area of the substrate, forming a second conductive type well in a second active area of the substrate, and filling up the trench with a dielectric.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices and, moreparticularly, to methods of forming wells in semiconductor devices.

BACKGROUND

Generally, in semiconductor device fabrication, well implantation iscarried out after completion of shallow trench isolation (STI), STIfilling, and STI planarization. FIGS. 1A to 1F are cross-sectionaldiagrams for explaining a known method of forming a well in asemiconductor device. Referring to FIG. 1A, a pad oxide layer 11 isgrown on a silicon substrate 10 by thermal oxidation. A pad nitride(SiN) layer 12 and a pad tetraethylortho silicate (TEOS) layer 13 aresequentially deposited on the pad oxide layer 11.

Photoresist is coated on the pad TEOS layer 13. Exposing and developingare carried out on the photoresist layer to form a photoresist pattern14 exposing a prescribed surface of the pad TEOS layer 13 correspondingto an STI area for semiconductor device isolation. The pad TEOS,nitride, and oxide layers 13, 12, and 11 are etched to expose a portionof the semiconductor substrate 10 using the photoresist pattern 14 as anetch mask. The exposed portion of the semiconductor substrate 10 isetched to form a trench 15.

Referring to FIG. 1B, after the photoresist pattern has been removed, anadditional etch is carried out for STI rounding and divot depthadjustment. Further, referring to FIG. 1C, an oxide layer 16 is formedon an inside of the trench 15. Referring to FIG. 1D, a dielectric layer17 is formed on the pad TEOS layer 13 to fill up the trench 15.

Referring to FIG. 1E, planarization including chemical mechanicalpolishing (CMP) is carried out on the dielectric layer 17 until the padnitride layer 12 is exposed. As shown in FIG. 1F, the pad nitride layeris removed to expose the pad oxide layer 11 so that the dielectric layer17 remains to fill up the trench only. Hence, an STI layer 17 iscompleted.

Referring to FIG. 1G, a photoresist pattern 18-1 exposing an n-well areais formed over the substrate 10. An n-well ion implantation is carriedout on the substrate to form an n-well 19-1 in an active area of thesubstrate 10.

Referring to FIG. 1H, a photoresist pattern 18-2 exposing a p-well areais formed over the substrate 10. A p-well ion implantation is carriedout on the substrate to form a p-well 19-2 in another active area of thesubstrate 10. Hence, final profiles of the n-well 19-1 and p-well 19-2are completed.

However, according to the known method, a profile for a peak point of adopant implanted by the well ion implantation is changed as shown inFIG. 1I. Namely, the dopant penetrating the STI layer 17 is unable toform a deep dopant profile. Additionally, the well peak point failing tobe formed deep under the STI layer works as a leakage point to increasethe current leakage between the bulk and junction, whereby semiconductordevice performance is degraded.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1I are cross-sectional diagrams for explaining a knownmethod of forming a well in a semiconductor device.

FIGS. 2A to 2G are cross-sectional diagrams of semiconductor structuresfor explaining the disclosed methods of forming a well in asemiconductor device.

DETAILED DESCRIPTION

Disclosed herein are methods forming wells in a semiconductor device, inwhich a well end point under a trench is formed deeper than another areaby well implantation prior to trench filling, thereby minimizing leakagecurrent.

Referring to FIG. 2A, a pad oxide layer 21 is grown on a siliconsubstrate 20 by thermal oxidation. A pad nitride (SiN) layer 22 and apad TEOS layer 23 are sequentially deposited on the pad oxide layer 21.Photoresist is coated on the pad TEOS layer 23. Exposing and developingare carried out on the photoresist layer to form a photoresist pattern24 exposing a prescribed surface of the pad TEOS layer 23 correspondingto an STI area for semiconductor device isolation.

The pad TEOS, nitride, and oxide layers 23, 22, and 21 are etched toexpose a portion of the semiconductor substrate 20 using the photoresistpattern 24 as an etch mask. The exposed portion of the semiconductorsubstrate 20 is etched to form a trench 25.

Referring to FIG. 2B, after the photoresist pattern has been removed, anadditional etch is carried out for STI rounding and divot depthadjustment.

As shown in FIGS. 2C and 2D, an oxide layer 26 is formed on an inside ofthe trench 25 and a photoresist pattern 27-1 exposing an n-well area anda half of the trench 25 is formed over the substrate 20. An n-well ionimplantation is carried out on the substrate to form an n-well 28-1 inan active area of the substrate 20.

Referring to FIG. 2E, a photoresist pattern 27-2 exposing a p-well areaand the other half of the trench 25 is formed over the substrate 20. Ap-well ion implantation is carried out on the substrate to form a p-well28-2 in another active area of the substrate 20. Hence, final profilesof the n-well 28-1 and p-well 28-2 are completed. In doing so, a wellend point formed under the trench is formed deeper than that of therelated art to elongate a leakage path, whereby leakage current betweena junction and a bulk of the silicon substrate 20 is minimized.

Referring to FIG. 2F, a dielectric layer 29 is formed on the pad nitridelayer 22 to fill up the trench. Planarization including CMP is carriedout on the dielectric layer 29. As shown in FIG. 2G, the pad nitridelayer is removed to expose the pad oxide layer 11 so that the dielectriclayer 29 remains to fill up the trench only. Hence, an STI layer iscompleted and a prescribed transistor is formed on the correspondingactive area.

As disclosed herein, a well end point under a trench is formed deeperthan other area by well implantation prior to trench filling, a well endpoint under a trench is formed deep, and an active area is protected bya thin nitride layer. Therefore, a leakage path is formed longer underthe trench to reduce a damage of the active area and leakage current isminimized.

Further, as disclosed herein, well ion implantation is carried out priorto filling a trench with a dielectric and amendment of equipments orprocesses is minimized to be directly applicable to production, wherebyleakage current is minimized without additional investment.

According to one example, a disclosed method forming a well in asemiconductor substrate may include forming a trench in a surface of asubstrate to define a field area, forming a first conductive type wellin a first active area of the substrate, forming a second conductivetype well in a second active area of the substrate, and filling up thetrench with a dielectric.

In one example, the first and second active areas are isolated from eachother by the field area. The first conductive type well forming mayinclude forming a first ion implantation mask on the substrate to exposethe first active area and a first half of the trench in the vicinity ofthe first active area, implanting a first conductive type dopant intothe substrate exposed by the first ion implantation mask, and removingthe first ion implantation mask.

The first ion implantation mask may be formed of a first photoresistpattern. The second conductive type well forming may includes forming asecond ion implantation mask on the substrate to expose the secondactive area and a second half of the trench in the vicinity of thesecond active area, implanting a second conductive type dopant into thesubstrate exposed by the second ion implantation mask, and removing thesecond ion implantation mask.

Further, the second ion implantation mask may be formed of a firstphotoresist pattern. In one example, well end points of the first andsecond conductive type wells may be formed under the trench to be deeperthan bottoms of the first and second conductive type wells in thecorresponding active areas, respectively.

This application claims the benefit of the Korean Application No.P2003-0100550 filed on Dec. 30, 2003, which is hereby incorporated byreference.

Although certain apparatus constructed in accordance with the teachingsof the invention have been described herein, the scope of coverage ofthis patent is not limited thereto. On the contrary, this patent coversevery apparatus, method and article of manufacture fairly falling withinthe scope of the appended claims either literally or under the doctrineof equivalents.

1. A method of forming a well in a semiconductor substrate comprising:forming an STI trench in a surface of a substrate to define a fieldarea; forming a first ion implantation mask over the substrate and thetrench such that a first active area and a first part of the trench areexposed; forming a first conductive type well in the first active areaof the substrate and under the first part of the trench so that an endpoint of the first conductive type well under the first part of thetrench is deeper than a bottom of the first conductive type well in thefirst active area; forming a second ion implantation mask over the firstactive area and the first part of the trench; forming a secondconductive type well in a second active area of the substrate and undera second part of the trench so that an end point of the secondconductive type well under the second part of the trench is deeper thana bottom of the second conductive type well in the second active area,wherein the first and second conductive type wells meet under the trenchand the end points of the first and second conductive type wells wherethe first and second conductive type wells meet are deeper than bottomsof the first and second conductive type wells in the first and secondactive areas; and filling the trench with a dielectric after forming thefirst and second conductive type wells.
 2. A method as defined by claim1, wherein the first and second active areas are isolated from eachother by the field area.
 3. A method as defined by claim 1, whereinforming the first conductive type well comprises: implanting a firstconductive type dopant into the substrate exposed by the first ionimplantation mask; and removing the first ion implantation mask.
 4. Amethod as defined by claim 3, wherein the first ion implantation maskcomprises a first photoresist pattern.
 5. A method as defined by claim1, wherein forming the second conductive type well comprises: implantinga second conductive type dopant into the substrate exposed by the secondion implantation mask; and removing the second ion implantation mask. 6.A method as defined by claim 5, wherein the second ion implantation maskcomprises a first photoresist pattern.
 7. A method as defined by claim1, wherein the semiconductor substrate comprises a silicon substratehaving a thermal oxide layer thereon.
 8. A method as defined by claim 7,wherein the semiconductor substrate further comprises a silicon nitridelayer on the thermal oxide layer.
 9. A method as defined by claim 1,wherein the semiconductor substrate comprises a silicon substrate havinga silicon nitride layer over the first and second active areas.
 10. Amethod as defined by claim 8, wherein the semiconductor substratefurther comprises a TEOS layer on the silicon nitride layer.
 11. Amethod as defined by claim 1, wherein the semiconductor substratecomprises a silicon substrate having a TEOS layer over the first andsecond active areas.
 12. A method as defined by claim 1, furthercomprising forming an oxide layer on an inside surface of the trench.13. A method as defined by claim 12, wherein the oxide layer is formedprior to forming the first and second conductive type wells.
 14. Amethod as defined by claim 1, further comprising planarizing thedielectric by chemical mechanical polishing.
 15. A method as defined byclaim 8, further comprising planarizing the dielectric by chemicalmechanical polishing.
 16. A method as defined by claim 10, furthercomprising planarizing the dielectric by chemical mechanical polishing.17. A method as defined by claim 15, comprising sufficient chemicalmechanical polishing to remove the silicon nitride layer.
 18. A methodas defined by claim 1, wherein filling the trench with the dielectriccomprises depositing dielectric material on the semiconductor substrate.19. A method as defined by claim 1, wherein forming an STI trenchcomprises: forming a photoresist pattern to define an area of the trenchand exposing a surface of the TEOS layer, and etching the TEOS layer,the silicon nitride, the oxide layer, and the silicon substratesequentially to form the STI trench.
 20. A method as defined by claim19, further comprising STI rounding by additional etching of the trench.